Integrated circuit capacitors are widely used in integrated circuit devices. For example, in Dynamic Random Access Memory (DRAM) devices, integrated circuit capacitors may be used to store charge thereon, and thereby store data. As the integration density of integrated circuit devices, such as DRAM devices, continues to increase, it may be desirable to maintain sufficiently high storage capacitance while decreasing the area of the integrated circuit substrate that is occupied by each capacitor.
In order to increase the amount of capacitance per unit area of the integrated circuit substrate, it is known to use three-dimensional capacitor structures that can increase the effective area thereof. One type of three-dimensional capacitor structure is a cylindrical capacitor. Cylindrical capacitors are well known to those having skill in the art and are described, for example, in U.S. Pat. No. 6,258,691, entitled Cylindrical Capacitor and Method for Fabricating Same, assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
As is well known to those having skill in the art, an integrated circuit capacitor generally includes a first or lower electrode, also referred to as a storage node, a dielectric layer on the first or lower electrode, and a second or upper electrode on the dielectric layer opposite the first or lower electrode. In a cylindrical capacitor, at least part of the lower electrode is cylindrical in shape.
A conventional semiconductor memory device having cylindrical capacitor lower electrodes and a conventional method of manufacturing the same will be described with reference to FIGS. 1 and 2. As shown in FIGS. 1 and 2, an interlevel insulating layer 110 is deposited on a semiconductor substrate 100 having semiconductor devices (not shown) such as metal oxide semiconductor (MOS) transistors. Storage node contact plugs (hereinafter referred to as contact plugs) 115 are formed in the interlevel insulating layer 110.
Capacitor lower electrodes 120a and 120b having cylindrical shapes are formed on the contact plugs 115 and predetermined portions of the interlevel insulating layer 110. The capacitor lower electrodes 120a and 120b are composed of bottoms 120b, which are electrically connected to the contact plugs 115 and sidewalls 120a, which extend from the bottoms 120b upward, to a predetermined thickness, so as to be perpendicular to the bottoms 120b. The capacitor lower electrodes 120a and 120b, i.e., the bottoms 120a enclosed by the sidewalls 120a may be circular, elliptical, or polygonal such as rectangular. Spaces in the sidewalls 120a are vacant and open. A dielectric layer and capacitor upper electrodes are formed on the resultant structure so as to complete the capacitors.
A method of manufacturing the capacitor lower electrodes 120a and 120b that are cylindrically shaped will now be briefly described. First, an etch stopper (not shown) and a mold oxide layer (not shown) are sequentially deposited on the interlevel insulating layer 110 having the contact plugs 115. The mold oxide layer is formed to a thickness of about 15,000 Å. The mold oxide layer and the etch stopper are selectively etched using photolithography and an etching process so as to define areas in which capacitor lower electrodes will be formed. The contact plugs 115 are exposed in the areas in which the capacitor lower electrodes will be formed. Next, a conductive layer (not shown) is conformally deposited to a predetermined thickness in the areas in which the capacitor lower electrodes will be formed and on the mold oxide layer, and then a buffer dielectric layer (not shown) is deposited on the conductive layer.
Thereafter, the buffer dielectric layer and the conductive layer are etched until the surface of the mold oxide layer is exposed so as to separate nodes of the conductive layer. For the etching process, Chemical Mechanical Polishing (CMP) and/or dry etch back is used. Remaining portions of the buffer dielectric layer and the mold oxide layer are removed using wet etching so as to make the capacitor lower electrodes 120a and 120b cylindrical.
Unfortunately, capacitors including the capacitor lower electrodes (120a and 120b) which are cylindrical may have the following problems. As the density of the devices increases, areas of the bottoms 120b may continue to be reduced. Thus, if heights of the sidewalls 120a do not increase, capacitors having a desired capacitance may not be obtained. However, when increasing the heights of the sidewalls 120a in order to increase the capacitance, the entire arrangement of devices formed under and over the capacitors may change. Moreover, if the heights of the sidewalls 120a are too great, the ratio of the heights of the sidewalls 120 to the widths of the bottoms 120b may be too great. Due to this aspect ratio, the capacitor lower electrodes 120a and 120b may become slanted, which may cause the semiconductor device to have defects.